In a dynamic random access memory cell having a one-transistor/one-capacitor structure, one of current terminals of an access transistor is connected to a bit line and another one is connected to a storage electrode of a capacitor. In usual, two gate electrodes are provided on a single active region and three source/drain regions are formed such that one of the source/drain regions is located between the gate electrodes and two of the source/drain regions are located outside the gate electrodes, whereby two transistors are formed. The middle source/drain region is used as a common bit line connection region and the outer source/drain regions are connected to capacitors, whereby two memory cells are formed.
Known capacitor structures are a planar type, a trench type, a stack type, and the like. Known isolation techniques are local oxidation of silicon (LOCOS), trench isolation, and the like.
In order to reduce the area occupied by a single memory cell to increase the integration density of memory cells, the area occupied by a single transistor and the area occupied by a single capacitor need to be reduced.
Japanese Laid-open Patent Publication No. 3-142872 discusses that a capacitor is provided on a sidewall of a trench for isolating an access transistor and the trench is used for two purposes: isolation and capacitor mounting.
Japanese Laid-open Patent Publication No. 6-318679 discusses that a local-oxidation-of-silicon (LOCOS)-type field insulating layer defining active regions is formed, transistors are formed in the active regions, a trench is formed around each active region adjacent to the transistors every memory cell, an impurity diffusion region is formed in the trench and coated with a dielectric layer, a counter electrode is formed on the dielectric layer, another dielectric layer and a storage electrode are deposited on the counter electrode in that order, and thereby a capacitor in which the counter electrode is sandwiched between the impurity diffusion region and the storage electrode is formed.